The basic production methodology involves three main parts: design, implementation and verification (or testing). Testing takes a large quantity of the time and effort in the design, production and use of digital circuits. Testing determines whether or not the chip was manufactured without harmful defects known as faults. Faults may arise because of defective components such as logic gates, memory elements, etc. Faults may also be due to breaks or shorts in interconnections, or a number of other reasons.
To accomplish testing of ICs, a variety of testing methods and techniques have been developed in the prior art. Today, since the number of circuits that can be integrated into a chip is very large, many ICs have the testing circuitry integrated on the same chip. These testing circuits are commonly referred to as "built-in" testing circuits. When a "built-in" test operates to test the circuitry by itself, it is commonly referred to as a "built-in self-test" (BIST).
Every BIST system has two basic parts: one part provides the stimulus, or test data, for testing the custom circuit and the other collects the responses to the applied stimulus to verify whether they are correct. The stimulus can be any pattern of data that would be efficient in testing the circuit. Typically, random values are used and propagated through the logic. The custom circuit acts or "responds" to the stimulus values. The responses to the stimulus are collected.
The number of responses involved is too large to compare directly with known good responses. The responses are compressed using a variety of techniques in the art. The compressed responses are accumulated to create a statistic. After testing, the statistic is compared with a reference statistic which is known to be good. If a match exists, the circuitry is deemed to be functioning properly.
BIST technology has been employed to test both combinational and sequential logic circuits. A circuit is combinational if its output is solely a function of its current input. A circuit is sequential if its output is a function of the current input and its current state. Sequential logic circuitry that holds its current state for use with future input data is commonly referred to as "memory" or "storage" circuitry.
Testing of combinational circuits is easier in comparison to sequential logic circuitry. In testing the combinational circuit, the only inputs to the logic are stimulus valves. Since combinational circuits do not have states, the responses are only dependent on the current stimulus values. Testing of sequential circuits, on the other hand, is difficult because the resulting behavior (i.e. responses) of a sequential circuit depends not only on the stimulus valves input into the circuit, but also on the current state of the logic. To obtain accurate responses, the current states of the memory elements must be controlled and observed. However, this quickly becomes impractical where the number of memory elements is anything more than minimal. Furthermore, this requires excessively long test sequences, which undesirably lengthens the time to complete production of the custom chip.
The memory elements of a sequential circuit can be isolated and controlled, thus reducing the circuit to one which is combinational. This approach is beneficial since test generation is reduced to the combinational case. One such application of the simplification was the use of a BIST flip-flop cell for replacement of a D flip-flop (Stroud, "Automated BIST for Sequential Logic Synthesis," IEEE Design and Test of Computers, December. 1988).
This technique, however, has been limited in the prior art, namely due to the fact that suitable replacement circuitry could not be found for certain memory elements. For instance, logic subject to an asynchronous reset could not be tested in this manner. The present invention proposes circuitry to allow testing of sequential logic having asynchronous resets.
Furthermore, other problems exist which are associated with replacing memory elements with equivalent circuitry. For instance, during self-testing, all memory elements must be clocked off the same signal. However, some memory elements receive these clock signals from gated logic or other flip-flop circuitry. Thus, circuitry is required to allow all the memory elements to be clocked from the same clock during self-test, while allowing the circuitry to function normally when carrying out its designated logic function.
Finally, tri-state drivers allow multiple devices to have access to the tri-state buses. Normally, two or more drivers do not "fight" over ownership of a bus. However, during self-testing, these "drive fights" can occur. Moreover, it is important that all signal values in the circuit be well-defined. In view of these considerations, there is a need for tri-state buses to be driven to a known state during testing.
Hence, the present invention provides equivalent circuits to replace existing logic circuits. The replacement circuitry of the present invention allows the circuitry to be tested when in self-testing, while being able to perform is normal function during user mode.